Design Of 1200V SiC MOSFET Devices

As one of the representatives of the current popular wide band gap semiconductors,Silicon Carbide has excellent characteristics of high critical breakdown electric field and high thermal conductivity.It is one of the options to replace traditional Si materials and promote the further optimization and development of power devices.Due to the late start of Si C devices,the Si C material parameters measured at present are not accurate enough,the construction of physical model is not complete,and the process technology is not as advanced as Si,which makes there is a large gap between the simulation results of Si C and the actual Tape-out results.It will increase the research and design cost to a certain extent.Therefore,calibrating Si C simulation model has certain significance to reduce device design cost.In addition,compared with Si,Si C has a higher critical breakdown electric field,so the electric field of gate oxide in Si C is also high,which leads to the device reliability problem.In order to give full play to the advantages of Si C material,it is necessary to design the reliability of the gate oxide in Si C and find a process method to optimize the high interfacial state density of Si C/Si O₂ during device design.The main work content of the thesis is as follows:Firstly,the impurity distribution results of Si C substrate after ion implantation,the thickness of oxide film grown by thermal oxidation,Si C MOS capacitance and Si C MOSFET were obtained by Tape-out.Then the interfacial state density of Si C/Si O₂ and channel mobility of Si C MOSFET were extracted respectively.The physical model was built by simulation tool and then corrected by Tape-out results.More accurate ion implantation model,interface state physical model and mobility model were obtained after fitting modification,and then the calibrated simulation tool was used for device simulation design.After the basic structural parameters of the device are determined to meet the design index,the variation law of electric field in gate oxide and specific on-resistance is studied by adjusting the width of the JFET region,and the optimum JFET region width is selected for further optimization design.In order to optimize the device performance,the current spread layer is added to the original device structure,which further reduces the specific on-resistance while ensuring the breakdown voltage.Finally,a central-implant P+structure is added to share the electric field lines terminated at the gate electrode,thus reducing the electric field in the gate oxide.Finally,the traditional Si C MOSFET sample with breakdown voltage of1635.33 V,threshold voltage of 2.29 V and on-resistance of 130.67 mΩwas obtained through Tape-out.The test results were compared with the simulation results to verify the validity of the simulation model calibration.