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The Power Management Design For Mobile Terminal Devices Based On Windows CE

Posted on:2010-07-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y YeFull Text:PDF
GTID:2178360272979105Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Embedded systems are now parts of our daily life; they are used almost everywhere, like satellites, PDA, cellular phones, mp3, etc. Most power supplies of embedded systems are rechargeable batteries, though the technology of battery increases the power that battery could store, the increasing demands of people make the power of embedded systems become more and more dissipative. So, we need effective power managing technology to save as much power as possible while still satisfies performance requirement and user experience. In software, various DPM technologies have been found out; in hardware, PM (Power Management) has been taken into account when system designing by various OEMS, which is more convenient for software algorithm of PM. The most representative PM architecture is one of Intel Xscale's. It supports DVPM, DFM and PMU servicing for judging current system load in hardware. It also provides some APIs for controlling power states of system.The concrete work described in the thesis is as follows:1. Design a Product level PM architecture combined WPM (Windows Power Manager) with IPM (Intel Power Manager) in one famous mobile develop company's smart phone project, the first domestic dual mode (GSM/PHS) smart phone with mobile television based on ARM10 (Intel Xscale PXA300) microprocessor and WINCE5.0 OS.2. Part memory refreshing technology is introduced according to hardware features of Intel Xscale architecture, which reduces more RAM power consumption in system standby and sleep states. 3. The DVFS of Intel IPM is studied chiefly for finding out DVFS algorithm suitable to this project platform, in order to economize more energy on the basis of not affecting system performance.
Keywords/Search Tags:dynamic power management, embedded system, Xscale architecture, partial memory self refresh, effect of power saving
PDF Full Text Request
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