The Design Of Fieldbus Communication Controller

Fieldbus is a process for manufacturing and automation equipment for local area networks. The network itself has the ability to achieve the distributed automatic control. Fieldbus communication protocols are the core issues to deal with this achievement. Communication protocols are used to achieve connectivity between the computer and network standards. Fieldbus instruments are on the network node, and have similar functions as other traditional instruments at the same time. Fieldbus communication controller is the core component of Fieldbus instrumentation. This proposal is to study the contents of design methods about fieldbus communication controller and technology associated with improvements.Paper presents an improved version about the idea of fieldbus communication controller. Because of the rapid development of electronics industry, single-chip function becomes increasingly powerful, and it has been able to replace the existing communications controller in many functions, such as direct memory access (DMA) functions. But most of the existing single-chip microcomputer, such as SPI, I2C and other serial expansion of technology, existing communications controller makes the parallel port to become redundant. Therefore, the design of a simple functional structure of fieldbus communication controller with a serial interface is necessary.First of all, paper starts from a practical point of view. After the detailed analysis of existing fieldbus communication controller and the single-chip based on the functional structure, it concluded that only the receiver which contains the Manchester encoding and decoding functions and CRC checksum function communications controller is the best choice. As a result of eliminating a number of modules, the design cycle could be made significantly shorter. Instead, the serial interface allows the use of I / O PAD significantly reduce the quantity, making the cost much lower.After a detailed analysis of the receiver based on the principle, paper gives the communications controller in the overall architecture, and it was further defined after the design concept. Paper also sets off the entire design in accordance into several general functional modules which are Manchester decoder, encoder, receiver CRC checksum, and send CRC checksum circuit. After conducting each module to further in-depth and detailed analysis, it comes up with the corresponding state transition model, which gives a specific design. After designing the specific chip studied in this paper, first to write RTL code and their functional simulation and to perform the logic synthesis, and then proceed through the synthesis of the schematic diagram, area, and timing, such as analysis of the reports, obtained to reduce chip size. Finally, the project is designed to enhance cost-effective.