A Design Of Embedded Verification System Based On JTAG And FPGA

As semiconductor manufacturing technology continues to progress,SOC (System On a Chip) are the future of IC industry,the focus of technology research. Due to the growing complexity of SOC design,and chip size increases,the complexity of the chip functionality increases,the design verification work has become even more cumbersome.Functional verification of complex ASIC design has become the biggest bottleneck in design.ASIC using FPGA system designs functional verification is to use FPGA devices to verify the design of the user question.Using of test vectors or through the target system to produce a true incentive,validates and tests chip logic function. Through the using of FPGA systems,in the ASIC design beginning,it is easy to verification of chip design capabilities,supporting for hardware,software and the parallel development of the whole system and check the hardware and software compatibility.At the same time,it can also be tested in the target system running the actual software.FPGA simulation prominent advantages are speed,and users can design the necessary real-time simulation of a variety of input excitation.The SOC verification needs to deal with some real-time data.And the advantages of FPGA as a hardware system are speed,real-time good.So SOC can debug system software and design ASIC at the same time.This design uses the ALTERA company's FPGA as the main body to build verification systems hardware platform,by adding in FPGA embedded soft core processor NIOSⅡand customized JTAG(Joint Test Action Group) Logical Construction and Commissioning of PC data link verification,and using improved JTAG logic generated test vectors.JTAG controls of the target system Soc, achieves online testing and verification to the internal of SOC and other IP (Intellectual Property).At the same time,the verification platform can also support follow-up SOC target system software development and debugging.This paper introduces the chip verification system,including system performance,composition,functions and working principle;structures JTAG and FPGA-based SOC verification of embedded systems hardware platform.This paper presents the overall design program of the verification system.This article focuses on the data link verification system.In this paper,a detailed study of embedded soft core processor NIOSⅡsystem.In this paper,the custom logic and JTAG processor NIOSⅡcombine to build a debugging and verification of data link.In accordance with the requirements of chip verification,this paper designs the soft-core processor NIOSⅡsystem and sets up PC data link software systems,and completes the online test and verify to the chip.The overall mission of this topic is the use of FPGA and custom JTAG scan chain technology,to complete a certain type of Chinese-made DSP chip verification and testing,to research how to build a universal chip SOC verification platform to solve the problem which refers the verification system of reusable and real-time, accuracy,observation during data sent,transmitted,collected.In this paper,the SOC verification system in the application field research of the chip verification and testing has a higher theoretical and practical research value.