The Logic Design And Verification Of 8bit GFPT Protocol Based On OTN

The GFP(Generic Framing Procedure) is a new data transport procedure over optical Synchronous Digital Hierarchy Transport network.this can simplify the Hierarchy of Data over SDH,and can support many client signal.As the digital transport network changing from SDH network to OTN network,how to use the GFP which is the new generate data link layer procedure on the OTN transprot network,becomes to many company's important studying.Firstly,This paper is based on the implementation of Gigabit Ethernet Over OTN technology with GFP, and introduces the background of digital transport network.There is three generation of the digital transport network,The first one is T1/E1, the second one is SDH,and now is OTN,the developing trend of digital transport network is introduced.we analyze the procedure used in the paper,the procedure introduced is as following:IEEE 802.3 ethernet procedure,OTN transport network procedure,and GFP procedure.Secondly, The 2.5Gigabit OTN ADM(ADD/Drop Multiplexer) based on GFPT (Generic Framing Procedure Transparent) is introduced.by using modularize method,we give the GFPT over OTN ADM's function and data process flow,hardware design and how to select the chip used in the design.because the design is mainly based on FPGA, according to the used LUT,RAM,I/O and clock frequency, the selection of FPGA's type is importantly described.compared the altera's FPGA with the xilinx's FPGA, at last we choose the EP2SGX60C as the design's FPGA.Thirdly,According to the GFP procedure,we give the detailed design of GFPT based on FPGA.there are several sub_modules for the GFPT map/demap module. The module's function,the interface and timing diogram of every sub_module is distinct. By using the synchronous design method, one-hot state machine, asynchronous clocks domain process method, achieve the circuit design, and guide the verilog coding,then use the synplify tool to synthesis the code, achieve place and route with the quartusII tool, use the TimingQuest to achieve timing analysis, at last, get the sof file to the test on board.Fourthly,verifying the GFPT module with the white box verification way and black box verification way,and show the verification construction based on verilog.and then test the board's function in the network, implement the testcase for GFPT. according to the verified data, analyse the result referring to the function and performance.The final test result indicates the designed GFPT module achieves the functions such as superblock blocking and the number of the superblock can be configed . and the gfp map can achieve the standand of procedure.and the system can transport two channel of GE data,no package lost.