Design Of Test-Structure Layout Generator For Nanometer IC Design For Manufacturability Use

Integrated circuit process advances to super sub-micrometer and nanometer technology nodes, process variations influence the precision of devices and interconnect parameters, damages the function and yield of IC. Test structures layout automatically generation could generate the test structures layout files which were needed in the research work aiming at process variations and the influence to devices and interconnect parameters with high speed and efficiency, and is with active meanings.This thesis analyzed the current researching situation, introduced process variations and the influence to IC devices,interconnect and circuits. The thesis introduced the interconnect parameters and the influence of process variations and the charactering method. The thesis demonstrated the layout structures,principle and the objective parameters of the three types of test structures which were used in charactering interconnect parameters. The test structures generator aims at the three types of test structures, implements the test structures layout automatically generation by the program, according to layout layer information and test structures specification information. The generator program was implemented as program modules. The main program implements files inputting and the identifying,classifying and storing functions, controls the three subroutines to generate layout files of some special type. With the help of IC back-end tools, this generator could implement the checking and verifying of the generated test structures layout files.This thesis demonstrated the flow diagrams of the principle and the program of this generator, and some of the layouts generated. The operation of checking and verifying work shows that this generator can generate the test structures layout files automatically, efficiently and accurately.