Research On Test Chip Layout Automation And Yield Improvement Of Integrated Circuit

According to report by International Technology Roadmap for Semiconductors (ITRS), semiconductor industry has entered the "More than Moore" era, and the continued shrinking of physical feature size of integrated circuit has reached the stage of under 28nm. When the technology dimension steps into nanometer scale, the process of manufacturing becomes much more complex and the expensive, while the process defect caused yield loss and the design-based yield loss is becoming the most significant source of yield loss. Meanwhile, the number of design rules is rapidly increased with every node of technology circle and thousands of unique test structures per layer are needed to achieve yield characterization and detect process defect.In the other hand, IC fabrication costs are turning into extremely expensive. Multi-Project Wafer (MPW) integrates onto microelectronics wafers a number of different integrated circuit designs from various teams including designs from private firms, students and researchers from universities. It makes sense to share mask and wafer resources to produce designs in low quantities, which is enough for experiments and testing in prototype step. The costs are shared by all the teams according to the chip area, which would be 5%-10% of the cost of individual. MPW can lower the development risk and the threshold for market entry and human resource training. To achieve a proper reticle floorplanning, which can reduce the dicing cost and yield loss, is becoming one of the research hot spots of IC design. Focusing on test chip design and yield improvement, this thesis starts the following research work:1. According the characteristics of nanometer scale manufacture technology and request of data analysis of yield improvement, based on generic design rules of fabrication, we finish the parameterization for each type of test structures. Be prepared for test chip design automation.2. Based on the similarity of test structures and relation of different layers in fabrication design rules, we create a layout generator, and finishe layout auto-generation for various types of test structures as the design of experiment (DOE) demands In short-flow test chip, test structures are connected to PAD directly. We finish the modeling of placement and routing, and realize the auto placement and routing for short-flow test chip, which provides an efficient method of test chip layout design. 3. Addressable test structure array with more complex circuit and layout design has large volume of test structures, which has a strict request for layout automation. We present a modular unit based method of scalable test structure array design. By combining the device-under-test (DUT) and the switching devices into a standard modular unit, this method not only implements the four-terminal measurement to ensure the accuracy of the testing, but also significantly reduces mask consumption of test chips. The experiment results demonstrated that the process window can be tracked with those arrays, which further proves the accuracy and effectiveness of the presented design.4. After deeply analysis of the yield loss of chips in MPW caused by dicing, we present a novel simulated-annealing based floorplanning for MPW, which takes chip damage caused by dicing into consideration. This floorplanning method can reduce the dicing loss and improve the chip yield of MPW.