Design And Realization Of Instruction Unit Of X_DSP

The X-DSP is a high performance and low power 16-bit fix-point digital signal processor. It combines an advanced modified Harvard architecture (with one program memory bus, three data memory buses, and four address buses),a CPU with multiply /accumulate (MAC),compare,select,store unit (CSSU)application-specific hardware logic , on-chip memory, on-chip peripherals, a highly specialized instruction set,and it is fit for portable and embed application.As a participant to attend all course of this DSP, I design and realize the instruction control unit and interrupt control unit excellently. In this paper, a instruction unit is designed and optimized, it particularly introduces its logic design and verification of fetching unit, decoding and control unit, basing on thorough research of X-DSP instruction system and micro-architecture.Decoding matrix PLA is the key circuit of instruction unit, and it can realize the conversion from opcodes to micro-control signals.PLA can affect the size, speed and power consumption performance indexes of the instruction unit. In this paper, based on 0.25um CMOS technology, a decoding matrix PLA of X-DSP instruction unit is carried out in full-custom design, it particularly introduces the PLA's logic, layout, circuit design and verification,and analyses its performance. As another important component of the instruction unit, the interrupt can affect the performance of entire pipeline directly. Since speed is one of the most important indicators of its performance, we give a quick-responding interrupt system after making an intensive study of various technical implementations.At the end of this paper, the verification involving module and interrupt control system of our design is performed. The results of simulation show that our instruction unit can fully meet the technical requirements of X-DSP, which can also be well proved by the implemented chip.