The Design Of Ft-matrix Processor Instruction Set And Dispatch Unit

FT-Matrix is a high performance DSP designed by NUDT. It is mainly used for 3GPP-LTE baseband wireless communication. It is VLIW architecture with 16/32 variable length RISC instruction set, maximum instruction issued per clock is 10. The chip is divided into two parts: the scalar unit and the vector unit. The scalar part is designed to do the simple calculation and program loop control. The vector part is designed to provide most of the calculation ability. The number of instructions issued per clock and the variable length instruction set make the dispatch unit most complicated.To exceed higher performance of the dispatch unit, this thesis starts with application simulation. First optimize the function unit of the processor based on the analyses of the calculation statistics. Then I start with both soft and hard design, adjust instruction set pattern and optimize the dispatch unit logic, finally complete the design of the hight performance dispatch unit.This thesis includes achievements below:First, complete the 3GPP-LTE baseband simulation, aquire the calculation type and load statistics of the baseband system, provides envidence of the system architechture optimization.Next, analyse the relation between assembler and the dispatch unit, propose a methed to change the assembling time for the dispatch hardware complexity. Adjust the execution packet pattern by moving some of the dispatch unit's job to the assembler to simplify the dispatch unit.Then optimize the logic of the dispatch unit. Make the dispatch unit deal the instruction parallel information and the destination function unit information simultaneously. This new logic can shorten the critical path of the dispatch unit by 1/3. I also analyze some situation that makes the pipeline stall and give the solving method.At last this thesis provided the verification and synthesis result of the FT-Matrix dispatch unit, and the basic flow of system verification and synthesis.