Design And Implementation Of High Performance Low Power Embedded SRAM

The explosive development of semiconductor technology, high performance and low power design has become a major concern in recent years. Embedded SRAM is accounting for the large share of area in microprocessor and SOC, and has become the bottleneck of high performance and low power design now. So, it is important to design high performance and low power SRAM through full custom design method.To meet the design demands of two digital signal processors, this thesis analyzes and explores the design of embedded SRAM, focusing on delay and power optimization. The SRAM access path is split into two portions: from address input to word line rise (the decode path) and from word line rise to data output (the data path). Techniques to optimize both paths are investigated. In the decoding path, we present an optimal decoder structure which is different from the conventional structure for high performance low power SRAM, reducing the size of the input stage for good trade-offs between delay and power. The key to improve delay in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit-lines and the data lines. We investigate tracking circuits to limit bit-line and I/O line swings. The tracking circuits essentially use a replica memory cell and a replica bit-line to track the delay of the memory cell over a wide range of process and operating conditions. The self-timed technology is designed for the generation of the sense clock to enable sense amplifiers.Using custom design method, a 32kb (1k×32bit) low power embedded SRAM is completed and fabricated in 0.18μm CMOS process. The whole design flow including logic, layout and chip simulation and test design is completed. In typical case, the decode time is 388.23ps, and the access time is 1.23ns. The average power of reading and writing are 32.01mw.The design of a 600MHZ 0.13μm CMOS process high performance SRAM is also described, introducing the dual threshold voltage technique. The SRAM chip is about to tape-out, critical issues in function and performance test are presented. A scan test circuit configuration is described, effectively solving the multi-port problem during SRAM test. Not only saving the manufacturing validation cost, but also making sure the SRAM can be tested successfully. The simulation results show that the maximal access time under typical model is only 1.12ns, which meets the performance requirements.