Embedded 128kb Sram And Design

With the development of microelectronics the SRAM trends can be summarized as fast speed, large capacity and low power. In recent years, all kinds of chip embedded with SRAM is becoming more and more popular, which demonstrate excellent characteristics such as fast data store speed, high reliability and low dissipation power. In this paper a 128Kb full-CMOS SRAM is described which is embedded in a 32b MCU. Based on the analysis of the SNM and the SER, the device parameters of the 6T cell are optimized, which not only reduce cell size (the memory cell size is 10.8×14.8um2) but also make the SRAM more reliable (the SNM6T is 713mv). In order to improve the performance of the SRAM, array partition, divided word line structure and CMOS positive feedback sense amplifier are adopted. All of them not only improve the speed of the chip, but also reduce the power dissipation of the chip to the 1/8 compare with the traditional design. The access time of the SRAM is 20ns. The chip is fabricated by a double polysilicon, double metal and twin-well 0.6um CMOS process technology, and the chip size is 6.31×4.57 mm2. In addition, the chip can be configurated as a ×8b, ×16b or ×32b memory for the sake of convenience for the customer.