| As a new direction of the field of information science, and also the results of academic cross by emerging disciplines and traditional disciplines, wireless sensor networks has drawn the interest of Army, industry and academia all over the world. As the basis of wireless sensor networks, wireless sensor network node technology is essential. Because of its simple interface, low cost and good scalability, I~2C bus has been widely used in digital systems.By means of communication expansion of wireless sensor network nodes chip bus, the subject could communicate with more devices, and could make of more complex systerm, so that could further expand its scope of application. To achieve efficient, reliable and convenient serial communication with the external devices, the I~2C bus controller is connected to SFR bus which is in the wireless sensor network nodes chip. In the realization of the FPGA, the design of I~2C bus controller is mainly use Verilog HDL language. According to the low-power chip design idea of the wireless sensor network node, the I~2C controller is designed to add the choice of the clock module and stop signal to achieve the rapid and internal and external low-speed serial communication, so as to achieve the objective of reducing power consumption. Meanwhile, in order to further increase the flexibility of the system, the I~2C controller is designed to have master and slave model, and can achieve the conversion of two modes in different circumstances.The I~2C controller is designed under the treasury called Hua Hong NEC0.35. Timing Simulation has been made after DC synthesis. We can find from the simulation waveforms that data transmission is still ordered, stable and efficient after we added both low-power design and high-flexibility design to the systerm. The design is proved to be totally meet the need of both I~2C transfer norms and wireless sensor network nodes chip . The conversion between eight-bit serial data and parallel data can be made. |
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