Hardware Design And Implementation Of High Speed Bit Error Tester System Circuit Based On FPGA

High-speed BERT is mainly used in detecting for optical communication system, testing the error number of optical communication system and verifying the reliability of the system. In the optical communication system, the system BER performance is a very important indicator to measure of the system. It reflects the level of damaging of the digital information during transmission.The high-speed BERT system in this subject is mainly used in the optical communication system to test different rates of SFP optical modules and 9-pin optical module. It can also used in two test modes of human computer interface and stand-alone test. Given the low rate of costs of high-speed BERT overseas and singleness of function of high-speed BERT at home. In recent years, more and more optical modules are applied in optical communication systems, research and development the high-performance system is particular important. The development of this system is based on FPGA, the continuous BERT in this system can be up to 3.125Gbps. The following are the main aspects of this essay:1) To analyse how to implement the existing error testing:Software; FPGA and MCU; FPGA and external processing chip, etc. To apply FPGA to implement logic design and control circuit of the program.2) BERT system is based on FPGA and the external circuit, which requires power supply system voltage varity, voltage stability and power consumption. Through analysis of SPICE simulation, the system implement the design of DC/DC power supply and LDO. Finish the design of power sub-good board and the debugging aiming to meet the requirements of the entire power system.3) The system need to implement BERT of seven kinds of continuous rate. The clock system prove high requirements of fundamental frequency and jitter performance through the programs. Selecting the design of high-precision crystal oscillator input clock system can fully meet the requirements of the system.4) As a test system, the BERT system requires high jitter, through practical tests and analysis of theories, the system achieve fuction optimizing from the power system, clock system and PCB design respectively.5) The highest test rate of high-speed BERT system can be up to 3.125G Subjects were stacked from the PCB design,impedance control, circulation, and circuit termination circuit technology, and complete PCB design; high-speed circuits for signal integrity and power integrity simulation,to achieve design objectives. Finally, ebugging, high-speed BERT functions and performance optimization.The key parts of the paper is mainly about the power supply system and the clock distribution system of high-speed BERT hardware design based on FPGA. It also made some important analysis and design in the PCB of the system.Through the practical high-speed BERT system debugging, analysis of system performance, the system realize the optimization, finish the fuction of the entire high-speed test system and meet the requirements of test performance.