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Hardware Design And Implementation Of Qn PON Based Real-time Ethernet

Posted on:2011-08-20Degree:MasterType:Thesis
Country:ChinaCandidate:Q LongFull Text:PDF
GTID:2178360308452469Subject:Electromagnetic field and microwave technology
Abstract/Summary:PDF Full Text Request
Over years, the field bus technology applied in the field of industrial control is difficult to form a unified standard. It is difficult to resolve the issues of exchange and interoperability. Thereupon, Ethernet has begun to enter this field. The problem is that industrial control networks have the strict real-time and time-deterministic requirements, which are precisely the weakness of Ethernet. To solve this problem, Real-Time Ethernet (RTE) technology is proposed, with high real-time performance to meet the need in application.This paper introduces the Ethernet Passive Optical Network (EPON) into the industrial control field, and proposes real-time Ethernet passive optical network (REPON) based on multipoint passive optical network. Compared with the existing point-to-point real-time Ethernet, with the structure of multipoint-to-point PON, REPON achieves a better real-time performance. Meanwhile, realization of the hardware design and implementation of REPON nodes are based on FPGA (Field Programmable Gate Array), which can improve the capability of the real-time signal processing. This paper has made the related exploration and research for the hardware of REPON .The main contents are as follows:1) Design the network architecture of REPON, including PON-based network architecture, hierarchical communication model, as well as FPGA-based hardware system structure. REPON consists of a central node, multiple access nodes and optical distribution network (ODN), with each access node connected to a number of user services sub-networks. Every user can exchange real-time data through REPON.2) Design and implement the hardware of the center node and access node, which includes: design each functional module of the center node and access node; implement hardware circuit board of the center node and access node through the schematic design and circuit design; implement REPON 100Mbps physical hardware logic by increasing the control mechanisms of burst-data reception and transmit.3) Set up a reliable 100Mbps REPON-CAN experimental network on the hardware platform to verify the stability and reliability of the hardware system. The experimentation results show that this REPON hardware system can provide a stable and reliable performance, e.g. the bit error rate of its physical fiber link is less than 10 -9.
Keywords/Search Tags:Real-time Ethernet, PON, FPGA, CAN bus
PDF Full Text Request
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