Convolutional Coder And Viterbi Decoder Accelerator Design

There are ways mainly from two perspectives to measure the technical performance of wireless communication system. The quantity of communication system is judged by the validity and the quality of communication system is judged by the reliability. The purpose of channel coding is to improve the transmission quality of digital communication systems, and it always is a research hotspot in communication systems. The convolutional codes is used widely as channel coding. Convolutional code widely used in various digital communication systems, such as satellite communication systems, GSM,3G and so on. The decoding algorithms for convolutional codes are mainly the probability of decoding and algebraic decoding. Viterbi decoding in the decoding algorithm is the most widely used decoding algorithm for convolutional codes. In many chips of mobile communication terminals need to implement Viterbi decoding algorithm. So this paper focuses on Convolutional code and Viterbi decoding algorithm.This paper discusses the channel coding, the basic principles and methods of convolutional code and the basic principles of Viterbi decoding algorithm, while tail-biting convolutional codes and decoding methods are analyzed in detail. Based on describing Viterbi decoding in detail and summarizing the requirement of wireless communication systems, propose Viterbi decoding hardware accelerators and control the use of accelerators by registers to meet the mobile communication terminal chip system requirements. The input and output FIFO between the accelerator and chip is used to improve transmission efficiency and speed. Sliding window decoding process is used to deal with long decoding sequence. Design how to save branch metrics, state metrics and the surviving path memory to improve storage efficiency, coding efficiency and save chip resources. Implement the C-model of Viterbi decoding accelerator with C programming language in Microsoft Visual Studio 2005. Not only implement convolutional codes and Viterbi decoding algorithm, but also verify the correctness of Viterbi decoding algorithm. At last design test case to verify the design of this accelerator, summary accelerator performance and make the conclusion that the accelerator meets the requirement of GSM/GPRS system.