Convolutional Code Encoder And Viterbi Decoder Design

Channel is a very important part of a digital communication system. The characteristics of the channel affect the performance of the whole digital communication system. The noise and interference in the real channel make the codes received different from the codes sent. The difference is generally called error. In order to improve the quality of communication and ensure the reliability and validity of communication, error-control coding is usually adopted to correct the errors produced in the process of transfer before the digital signals enter the channel. The purpose of this thesis is to research how to improve the quality of transmission of digital communication system by error-control coding. This thesis focuses on a kind of channel codec arithmetic and its logic realization. And the channel codec arithmetic has been validated on hardware system based on FPGA.Error-control coding is an effective method to enhance the communication quality by adding redundant information into the original message. Convolutional code is a kind of error-correcting code which is used very widely. So, as the corresponding best decode method of the convolutional code, Viterbi decoder is always researched widely. This thesis discusses the coding arithmetic and the decoding arithmetic respectively. The emphases and difficulty are the researches on the Viterbi decode arithmetic and its logic realization. The top-down design method is adopted in the logic design process. And the function of the coder and the decoder has been proved to be correct.First, this thesis introduces the background of digital communication. Then it puts forward the error-control scheme, and gives a presentation of the arithmetic of (2, 1, 8) convolutional code and its corresponding decode arithmetic, the Viterbi decode arithmetic. After that, this thesis discusses the logic circuits of the traditional Viterbi decoder, and brings forward an improved logic design of the Viterbi decoder project.The thesis also introduces some basic design rules based on FPGA, and gives the report of the timing simulation. The design scheme of the hardware modules of the system is also presented in this part of the thesis. And the design of the whole hardware circuits has been completed. Finally, this thesis gives the process and the result of the system test on the hardware platform based on FPGA.Through the profound understanding of convolutional coding and Viterbi decoding, author describes the convolutional coding arithmetic and the Viterbi decoding arithmetic with Verilog HDL and implements them on Altera's Cyclone series FPGA. The maxim frequency of the coder is up to 275MHz, and the decoder is up to 92MHz. The outputted decoded data delays 65 symbol periods, and the speed of the output data is up to 118Kbps. The whole coding and decoding system can correct 6 errors in 64 continuous codes. In the hardware testing, the system works on 30MHz frequency, and it can code and decode correctly.