The Desin And Implementation Of Digital Predistortion Technology In WCDMA Repeaters

In the mobile communication system, we usually use power amplifier to enlarge the pow of the transmited signal in order to assure the Coverage in some range.Because power amplifier is inherently nonlinear,the nonlinearity creates spectral growth out of the signal bandwidth,which result in adjacent channels interferes.it also causes distortions within the signal bandwidth.For the characteristics of wideband and multi-carriers in the WCDMA system and OFDM,which make signal has high peak-to-average power ratios(PAPR).they are especially vulnerable to the nonlinear distortions bring from PA.In order to decrease the distortions,we must have the PA linearization technology in use.With the rapid development of the mobile communication business,both 3G commerce market and future 4G Prospects all propose high Principles to the PA linearization technology.Traditonal PA linearization technology solution is to back-off the signal pow from the PA saturation point, which assure the PA to work in its linear region.It is obvious that although the back-off solution is simple and high linearity,The PA efficiency would be cut down to very low.That is to say,in order to reach the rated output power,wo must provide the higher efficiency Amplifier Tube which will add the hardware cost. Consequently, it is not an optimal solution for the PA linearization technology.Digital Predistortion(DPD) technology characterized for its high performance,low cost, environmental has become the Contemporary mainstream PA linearization technology solution.In this paper,we mainly focus on DPD math foundation, performance simulation,the design and test of hardware solution.In the chapter 3,we mainly discuss the DPD simulation solution and result for the WCDMA signal with different carrier number on the MATLAB, which include float-point simulation and fixed-point simulation, finally give the simulation conclusion.The result of fixed-point simulation also provide the design basis for the FPGA implemention.DPD hardware solution which include both whole hardware system and FPGA design is discussed in chapter 4 in detail.We finally accomplish the FPGA implemention of the DPD algorithm.The system is a hardware-software co-design which leverages Xilinx FPGA features and embedded microprocessor technology. DPD filter is implemented on the FPGA with the LUT method which can save as much FPGA resources as possible. DPD coefficient estimate is implemented on the microprocessor embed in the FPGA. The final test results presented in the chapter 5 show 15 dB of improvement in adjacent channel power for WCDMA signals with different carrier numbers. Power amplifier efficiency is also improved, from 8% up to a maximum of 29%.