VLSI Design Of Motion Estimation And Motion Compensation For H.264/AVC Codec

H.264/AVC is the lastest video coding standard of ITU-T VCEG and ISO/IEC MPEG. This new standard was designed for the application in the area such as multimedia transmission, storage and searches. It adopted a lot of new technologies, such as multiple intra prediction modes, muti-mode high-precision inter prediction, multiple reference frame prediction, and 4×4 integer transform and content-based adaptive binary arithmetic coding. These new technologies can improve the accuracy of the image predictive coding, achieve higher coding efficiency. However, these new technologies greatly increase VLSI design complexity of motion estimation and motion compensation for H.264/AVC codec.Based on studying VLSI architectures of motion estimation and motion compensation for H.264/AVC codec, the dissertation proposed a macroblock-level three-stage pipeline VLSI architecture of motion estimation for H.264/AVC encoder and a motion compensation VLSI architecture based on the symmetry of interpolation algorithm for H.264/AVC decoder. The main work is as following:1,Proposed a macroblock-level three-stage pipeline VLSI architecture of motion estimation for H.264/AVC encoder by removing the data correlation to fully exploit the hardware parallelism of motion estimation. This structure reduces the needed clock cycles of the key module in motion estimation pipeline structure, and can effectively improve the performance of motion estimation. Proposed an optimized data storage strategy of reference frame by considering the re-activation feature wrap of SDRAM. This strategy effectively saves the cycles of wrap for accessing to SDRAM. Adopted a loop-storage method to achieve the memory sharing in macroblock-level three-stage pipeline VLSI architecture of motion estimation, which greatly saves the storage unit area.2,Designed a high-performance eight-position parallel processing VLSI structure of integer motion estimation based on segmented storage strategy. Design and VLSI implementation of each module was described in detail. The reference block data reading process was discussed based on the segmented storage strategy.3,Based on segmented storage strategy, a high-performance VLSI structure of fraction motion estimation was designed which adopts 1/2 and 1/4 pix motion estimation parallel processing. The VLSI implementation of each module was described, and the accessing process of the search window data was discussed in detail.4,Proposed a macroblock-level three-stage pipeline VLSI structure of motion compensation through making use of the symmetry character of the interpolation algorithm. VLSI structure and implementation of some key modules were discussed, including motion vector prediction module, reference data accessing module and interpolation module. An optimized motion vector prediction algorithm was adopted to regulate the data stream so as to be more suitable for hardware implementation. A new VLSI structure of lum interpolation module of separated 1-D approach was proposed based on the symmetry of interpolation algorithm, which can save 5 6-tap FIR filters and 6 register units of 8 bits compared with traditional separated 1-D approach.