The Design And Implementation Of 600MHz ALU Of YHFT-DX

YHFT-DX is a 32-bit fixing-point high performance DSP. Its architecture is VLIW and it can issue 8 instructions in a cycle. At TT corner using the 0.13um CMOS process, its CPU core can work at 600MHz steadily. This thesis analyzes deep the functions and the structure of the arithmetic logical unit(ALU), achieves ALU's design and implementation, its content is as follow:1. Detailed analyze the instructions and their functions of the ALU, the design is ulteriorly parted to some modules according to the principle of time-division multiplexing, and proposes the whole structure to reduce the area and power by hardware multiplexing. The timing budget is made to every module and the critical paths are found out. Execution stack with strict timing constraints uses the custom design approach, while decoding stack with relaxed timing constraints makes capital out of the semi-custom design approach based on the standard cell library.2. Using the custom design approach, design and implement the execution stack, to achieve improving the operation speed by about 50%. For the main operations 40-bit addition operation and 32-bit shift operation, analysis of the current adder and shifter structure, design and implement of the Sparse-Tree adder and the funnel shifter, obtain the compromise between speed and area at the structural level. Investigate the usage of circuit families deeply, analysis and implement some XOR gates and three-state gates, to improve the timing and area further at circuit level; transistor logic used in logical operations module, increase the speed of the circuit, reduces the area by 47%. After the completion of the logic design, achieve the implementation of the layout and extract its characterization parameters.3. Design and realize the decoding stack, using semi-custom design methods based on standard cell to improve the design efficiency and reduce the design cost. To meet the timing needs, customized the HLFF (hybrid lath-flipflop) trigger receives performance improvements. After achieving the design integration, the overall design was verified and the final test results are given.Via the above design, the final performance of arithmetic logic unit improves by about 50%, and reaches the design target working at 600MHz steadily.