Research And Design Of Adder Chip Based On 0.18um

The adding operation is the most basic operation in the arithmetic and logic unit(ALU).The adder circuit is an important building block for CPU.The optimization of speed,area and power consumption plays a very important role in improving high-performance chips.Improving performances of the adder has been a continuous effort for CPU designers.Adders mainly perform arithmetic functions in high-performance processors and are often stand in critical paths of circuits.In high-speed circuit design,the traditional standard cell design methodology is not appropriate because of speed requirements.However,a full custom design is often time and effort consuming,which is very expensive for design tasks with a tight tapeout schedule.To balance design effort and circuit performances,the building circuit blocks are optimized as much as possible to increase the speed.At the same time,in the layout design,a combination of semi-custom and full custom cell design methods are used to meet the design requirements,which greatly improves the design efficiency.Adders are studied in depth from algorithm level,structure level,circuit level and layout level.First,the structure of the traditional adder was compared,and the circuit structure of the Carry Lookahead was studied and compared.In the study of the Carry-Lookahead Adder,Kogge-Stone,Brent-Kung,Sklansky,and some improved structures were compared.Finally,a tree adder structure with relatively good area and speed based on Kogge-Stone algorithm was chosen.At the same time,the circuit used a hierarchical design,carry generation,carry propagation,point operation,and summation are all implemented by dynamic circuits.In order to solve the problem of charge leakage in dynamic circuits,a charge holder was designed for each domino node.The circuit cascade used domino logic,which not only isolated the internal and external capacitors,but also enhanced the stability of the circuit and prevents leakage.In terms of clock,in order to combine with the algorithm,the clock adopted a self-timed clock,which not only effectively improved the clock utilization rate,but also enable the 32-bit high-speed adder to achieve it its highest performance.The circuit is verified by Cadence simulation tools.For layout design,the characteristics of full customization and semi-customization were compared,and the area,speed,time schedule were compared.Finally,combining the advantages of semi-custom and full customization,the cell circuits were fully customized and automatically wired.And the GDSII was imported into the Cadence tool and verified via DRC and LVS.This method greatly improved the design efficiency.The design work is based on TSMC0.18um process,and used Cadence simulation tool for simulation.Under the condition of 1.8 V voltage and the load was set to 50fF,the delay was 1.576ns.