Design 2.5Gbps SDH Chip Interface Module

SDH(synchronous digital hierarchy) plays an important role in optical network. SDH interface standardization is the pivotal interoperability of different corporation's equipment. The interface of synchronous digital network on the network nodes was unified data interface specification, which makes the interface has the horizontal compatibility. SDH standard provides a standard set of bit rates and hierarchy, including STM-16 whose bit rates is 2.5Gbps, and this paper is designed for SDH cross-chip interface module, complete the following tasks.AU-side to the TU-side data uplink direction, AU-side of the input includes an asynchronous clock domain isolation, the data stream of fixed-byte fixed frame, descrambling, B1 checksum and error statistics, the frame header alignment, excellent protection of income, section overhead extraction, 2:4 protection of encoding, bit deslicing; TU-side output processing includes bit slicing, B1 insert and scrambling, the asynchronous clock isolation processing.From TU-side to air AU-side data downlink direction, TU-side inputs include asynchronous clock domain recovery, data framing, descrambling, B1 checksum and error statistics, the frame header alignment, bit deslicing; empty sub-cross-side output included bits slicing, 2:4 protection decoding, SOH and self-routing inserts to help protect concurrent, B1 insert and scrambling, asynchronous clock isolation.The interface module described in this paper is verified by the FPGA. Fully validated interface module as ZTE zx256940B SDH cross-chip interface part of the system clock frequency of 311M, which uses 90nm technics tapeout. The current ASIC sample tests are under way and the interface functional is correct.