The FPGA Design For Ionospheric Photometer

The Ionospheric Photometer is a new kind of optical instruments, which is used to detect the space environment. And it is one of the first optical remote sensing ionospheric instruments with high sensitivity at home. The electron density, the height of the ionosphere, O/N2 and other important information of ionosphere could be acquired by detecting 135.6nm radiation intensity of airglow at night and 135.6nm, LBH band radiation intensity during the day. The instrument is composed of telescope, filter wheel, detector and communication and control system.As the whole instrument’s master chip, FPGA is mainly responsible for controlling stepper motor, collecting pulses of photons, completing 1553 B communication, etc. The working state of FPGA directly affects if the whole instrument could operate efficiently and reliably in orbit.1553 B communication and stepper motor controlling are the key points and difficulties of the whole FPGA design.At first the paper introduced 1553 B protocol, and the realization of RT functions. Then methods of controlling stepper motor, including subdivision controlling technique and speed controlling method, were also discussed. On this basis, stepper motor control method which is suitable for driving Photometer’s filter wheel was presented. This method could suppress low-frequency vibration of filter wheel, improve control accuracy and ensure the motor running steadily and reliably.Based on needs analysis of the Ionospheric Photometer FPGA, the software’s function was decomposed and the design was divided into several entities and processes. In this paper,implementations and processes of each entity were introduced, and several methods to improve the FPGA design reliability were discussed.While the FPGA product was developed, the test was doing simultaneously. In addition to simulation and analyzing of entities and processes, other test methods were used to test the whole system. The results show that all the functions of the Ionospheric Photometer could be realized, and the FPGA design has the abilities of fault-tolerant and self-recovery.