Localization Receiver Design Based On FPGA For Locata System

As people continue to increase the demands of positioning, a variety of positioning systems emerged. The represented GPS satellite positioning system with its wide coverage and precision positioning ability, is currently the most widely used positioning system. But in indoor environment, due to the GPS signal loss is too large or sometimes completely cut off to make positioning. The pseudo-satellite technology can take on an important role in such situation, and can make users receive ranging signal in indoor environment.After deploying a network, traditional pseudolites usually suffer from "near-far" problem, particularly to the disadvantage of the co-positioning. And in the indoor environment, the multipath fading caused a massive signal loss. Overcoming these problems, as well as accelerating the development of positioning technology and engineering applications, would be with great theoretical and practical significance. Locata positioning system can solve the above problems and provides positioning services in all environments, it is becoming one of the hot research topics of pseudo satellite positioning technology. This thesis based on locata positioning receiver, its principles have been analyzed. The performance and implementation method of relative algorithms to solve "near-far" problem, multipath fading and high precision ranging is the focus of this thesis.Firstly, the present research status at home and abroad of pseudo satellite positioning technology and Locata technology is analyzed, and two generations Locata system are summarized based on the access to lots of literatures.Secondly, the components of the Locata positioning systeme are briefly introduced. Based on the detailed analysis on the three most important issues of Locata system, the solutions frame and algorithm is simulated in this thesis. The simulation results showed validity of these solutions.Again, a Locata receiver based on the front simulation are designed. The Hardware Architecture is "FPGA+MicroBlaze", include setup RF front-end parameters and program the driver process, use verilog and IP core to design intermediate frequency signal process module to acquisition and tracking signal.All hardware has been verified by simulation tools.Then, an operating system based on C language are designed, which for demodulate signal and output observation. At last, the matlab have been employed to verify the validity of design.Finally, the research work carried out in this thesis is summarized and the contents and recommendations for further research are given.