Design Of Digital Encrypted Lock Based-On Vhdl Language And FPGA

With the gradual improvement of the level of science and technology, the general mechanical lock hasn’t met the requirement for security guard.The digital encrypted lock(DEL) arises at the historic moment, and is used in the place whose security requirement is higher, such as banks and laboratories. The DEL is more and more popular.Using hardware description language (VHDL) on Altera company’s MAX-PLUSH platform,this design,whose the carrier is the field programmable logic device (FPGA), completes the subject of the hardware design, the function simulation and the timing analysis,which presents a digital encrypted lock design scheme.The DEL has many functions,such as the locking function, the unlock function, the password reset function, the clear and system alarm function. After the lock failed three times,the alert system alarms when it opens at the fourth time.This paper firstly introduces the working principle, the development direction and the design flow of FPGA, and the characteristics and structure of hardware description language (VHDL).Then six-digit digital encrypted lock is introduced detailedly in the design process and design content of each module.The design of the system in accordance with the process is divided into three parts, and the first part is the keyboard module circuit, including the clock generation circuit of the provision of the clock signal,the keyboard input circuit of Entering the password for the digital encrypted lock,the keyboard scanning circuit to produce digital combination through dynamic scanning and keystrokes,the keyboard decoding circuit of translating the digital combination into the function of each of the keyboard and the digital storage circuit to show the input password individually.The second part is a digital encrypted lock control circuit, including the digital lock key input circuit, the key function design circuit,the password lock-unlock and clear circuit and the alarm circuit.The third part is the display circuit, including six selected one data selection and seven segment digital tube display circuit.