Solid-state Short-circuit Current Limiter Engineering Research

The fault current has increased greatly along with the expanding power network and the complicated structure. This trend adds difficulty in installing system devices such as main transformer and breaker. So it is important to take effective action to limit fault current for the sake of the system security. In the recent years,supported by National Natural Science Foundation of China,the faculty in Zhejiang University have begun the research of solid states power switch and fault current limiting technology. They provide a novel solid states fault current limiting technology,which possesses flexible control mode. It is feasible to develop a well-performed fault current limiter.Based on this background,the author does some research on engineering application of the solid states fault current limiting technology. Firstly,the author introduces some examples of the increasing fault capacity in several area power systems of China. So it is necessary to make some research on fault limiter. Then the author gives an overview of some existing fault current limiting technologies and novel superconducting,solid states fault current limiting technologies. After that,the author discusses a novel solid states limiting technology and provides a single-phase solid states bridge current limiter and a main circuit topology of three-phase fault current limiter. It can be found that the new type of three-phase solid states bridge current limiter can handle the fault conditions more flexibly. It can not only remove the fault circuit,but also control the value of stable fault current to cooperate with the existing line three-segment relay. It also can realize soft reclosing under fault restoration. Afterward,the author gives a block diagram of a 380-voltage lab sample,the computation method of the main circuit parameters,the design of main hardware circuit and the part of the software realization in controlling circuit of the limiter. Finally,the author makes some introduction on the main disturbances appearing in the engineering design of the limiter and the measure of limiting those disturbances. The author makes a summarization about the problem in the on-site debugging which makes a preparation for the development of 10k-voltage novel solid states fault limiter.