Digital Down Converter Design And Implementation Of Automatic Gain Control Circuit

Digital Down Converter (DDC) is one of the core technologies in the Software Defined Radio (SDR) receiver. Its basic function is to pick up the narrowband signals from the broadband & high speed digital signals, and transform it to the baseband. Then the low speed baseband signals are sent to the following DSPs for processing.Automatic Gain Control (AGC) circuit is a kind of automatic control circuit. It can regulate the output-signal to some specified power level or limit it to a small range while the input-signal's power level is changing sharply. It is very important in communication equipments, especially in the receiving part. It controls the receiver's gain, ensuring the receiver has a high gain when a weak signal is received and a low gain when a strong signal is received.This thesis is based on the research project High Speed Dedicated DDC Based on FPGA, and it introduces the design and FPGA realization of an AGC circuit in DDC in detail. The main content is listed as follows:1. introduced the general principle and architecture of DDC, and the specified architecture, operational principle and arithmetic of DDC which is based on FPGA realization in the present project;2. introduced the architecture, principle and arithmetic of AGC circuit;3. described the design and realization of AGC module in DDC in detail, included submodule division, parameter setting, interface designing, timing designing, coding, simulation, and synthesis;4. presented strict verification and test result.The author of this thesis has implemented an AGC module in Altera's Stratix FPGA EPS40F1020C5 and this AGC module works well.