High Bit Rate Qpsk Demodulator Carrier Recovery Loop Algorithm And Implementation

With the rapid development of the space project these years, the requirement of real-time transfer data rate from the satellite to the ground is higher and higher. The data rate of the transmitter abroad is up to 1Gbps, and the data rate of the transmitter developed in China, can reach 600Mbps, but there is not a receiver in China, whose data rate can be as high as 600Mbps, or more than it. The research of high speed receiver is very important. The design of high speed demodulator is the main point of the high speed receiver. The design of carrier recovery loop is the key point of the high speed demodulator.This article first compares those frequently used carrier recovery algorithms, then pick out one algorithm, which is suitable for 100Mbps high speed QPSK carrier recovery, and implement it. In the second paragraph, kinds of carrier recovery loops frequently used are analysed in detail and compared. At the end, the hard-limited QPSK Costas loop is chosen. In the third paragraph, the hard-limited QPSK Costas loop is analysed in detail. The construction of the loop and the way to calculate the parameters of the loop are introduced. In the fourth paragraph, the design and test of the low speed QPSK carrier recovery are introduced. This paragraph tells us how to use EDA tools, for example ISE and CORE Generator to design the VHDL of the low speed carrier recovery loop by the Top-Down method, and how to test the design on xc2v1000 FPGA hardware, and the design is finally verified on hardware. The fifth and sixth paragraph introduce the design of the VHDL and hardware of the high speed QPSK carrier recovery loop, as well as the debugging and test of the high speed loop. As the VHDL of the high speed loop is similar to the low speed one, the key point is the hardware design and the system debugging. Finally, the FPGA based 100Mbps high speed QPSK carrier recovery loop is implemented.