Onboard The Bus Research And Application Of Solid-state Recorder

Missile-borne solid state recorder is one of the key equipments for dynamic parameters acquisition, information transmission and recording in missile flight test. According to the application background and the data stream characteristics of missile-borne solid state recorder, the dissertation puts forward the bus design principle and the modularization hardware structure.Based on the bus design principle and the modularization demand, the bus definition, the selection of connector, theory analysis and simulation of bus high-speed transmission, mechanism bus arbitration and high-speed data transmission logic design of the bus interface modules are described in detail. This accommodation bus structure has been applied in missile-borne solid state recorder, and the data transmission speed is 60MByte/s. At last, the dissertation introduces hardware circuit and logic design of the bus interface modules. The key technologies in this dissertation are generalized as follows:(1)According to the characteristics of missile-borne solid state recorder, the dissertation puts forward a accommodation bus which does not include address bus. The accommodation bus can easily satisfy the demands of large acquisition, large data transmission, sequential access, recording as a batch for missile-borne solid state recorder by few trough selection signal and simple logic design.(2)By theory calculation and simulation, the most fast speed of the global clock signal is 90MHz, this design adopts the bus frequency as 60MHz.(3)By quantitative analysis the difference of tradition data transmission method and source synchronization data method, the dissertation introduces the application of source synchronization data method in data storage and data reading processes which increase the data transmission speed inside the system.(4)In order to improving the condition of the inconsistency between data acquisition speed and storage speed, the bus interfaces of missile-borne recorder introduces high-speed buffer which is integrated in the FPGA by high-speed read-write operation between two buffers.(5)In the hardware design, the acquisition module accomplishes online channel programmable technology to satisfying the different test demand and environment,. By theory calculation, deposition of 16 pieces of flash memory chip in series and using circulatory writing technology are adopted in the storage module. This method can improve the storage speed greatly.