A Low Dropout Linear Regulator Design, The Active Frequency Compensation

Nowadays , the development of electronic technology is very rapid. The popularization of the portable electronic appliance has made a higher demand of the power management capability. The Power Management IC which has the highest integration, more intelligentized and function thus represents the main stream of the development of power management. The Power Management IC could operate with lower cost and higher efficiency. It can integrate multiple power system, thus it heightens the integration of system and provides more options to user.This dissertation developed a Low-dropout voltage regulator (LDO) which adopts an active-frequency compensation method. Firstly, the dissertation introduces the research actuality and development trend; then it analyses the LDO's structure and function. To seek the circuit parameter which influences the system operation, the LDO's transient response is construed. We acquired the factors which affect the system's loop stability by building the system's small signal model and analyze the frequency response. Also, the dissertation emphasizes the LDO's frequency compensation technology. It analyzes three frequency compensation methods of multistage amplifier (separate-pole approach, complex-pole approach and pole-zero cancellation) and the representative frequency compensation technology which base on above methods to be used in LDO's frequency compensation. Considering the factors which affect the system operation, this dissertation uses an active-frequency compensation method to compensate the LDO, it adopts dynamic-biased buffer impedance attenuation to decrease the buffer stage's output impedance so that the pole at the gate of the pass device is pushed to high frequency without dissipating large quiescent current, the active-frequency compensation generates an internal zero to replace the conventional capacitor ESR compensation and the effective capacitor multiplication can decrease the required on-chip capacitance. This dissertation analyses the function of the system's main modules and described the simulation results of whole system, moreover, it expatiates on the key point of IC layout.The IC is based on the 0.5um BCD process. Its input voltage range is 2.8V-8V, it has two output voltages, which are 1.8V and 3.3V respectively. Each LDO's quiescent current is 85uA; the load regulation is 3mV/1A, the line regulation is 3mV/4.2V. When the load current jumps from 1mA to 1A, the output voltage variation is controlled within 75mV. The test result indicates the design demand of circuit's capability is satisfied.