Based On Dynamically Reconfigurable Fpga Timing Circuit Line Fault Detection And Fault-tolerant Design

FPGAs are becoming more and more valuable for spacecraft electronic designers because of their high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. it is convenient for changing design on-orbit, even it can be applied for remote tolerance as result of reducing cost. Every coin has two sides, this non-permanent characteristic of FPGAs is prone to be interfered to causes problems with errors in the system.Circuitries based on SRAM FPGA are implemented by customizable logic cells. In cosmic radiation environment, that SRAM FPGA is hit by particles creates SEU, transient pulse occurs in the combinational logic caused by SEU turn to be a permanent effect, because the SRAM cell that implements that logic and routing has flipped. When SEU occurs in the sequential logic, it is a bit flip which can be corrected in the next sampling. A high efficient SEU immune circuit either can keep the transient pulse occurring in the combinational logic from storing or forbid bit flip appearing in storage cell. Most of existing methods mitigating SEU are based on time or hardware redundancy, or combine both of them. Full-time redundancy make use of the characteristics of the transient pulse, lath the output of combinational logic at three different times which separately delay d, then the right output is choose by voter. A full hardware redundancy, the well known TMR approach, has large area overhead which comes from additional sampling and the doubling the duration of the transient pulse which affects performance.Behavioral characteristic of SEU result standard tolerance approaches applied for ASIC system are not reliable, such as error detection and error correcting code. According to the different fault characteristic when SEU occurs in combinational logic and sequential logic, this dissertation proposed a new high level architecture for on-line detecting and correcting system based on SRAM FPGA which combined redundancy technique and dynamic reconfiguration characteristic of FPGA. Fault masking, fault detection, fault location and fault correcting are realized by this whole architecture without comprising system functionality.this dissertation start from background and meaning of the study, dicuss the special structure of FPGA and fault charatcteristic of circuit when FPGA in radiation environment in detail, then reviewed existing decteion technique and fault-tolerant technique, and then put forward the design idea of this dissertation, deeply elaborate design structure and design flow, at last exhibit the result of emulation and test to prove the correctness of design.