Hardware Design Of Deblocking Loop Filter In Avs Video Decoder

Digital video technology in the field of communications and broadcasting has been widely used, especially since the nineties in the twentieth century, with the Internet and the rapid development of mobile communication technology, the processing and transmission technology of video on the Internet and mobile networks have become China's information construction focus.In order to avoid high patent costs of H.264 international standards, satisfy the demand of information industrial development, in 2002, China began started to organize related enterprises and research institutes develop our own audio and video compression standards AVS.This paper reviews the development of AVS, introduces the characteristics, strengths, key technologies, as well as the significance of China's information industry.As the AVS standard block-based integer transform, quantization and motion compensation technology, inevitable the effect of blocking, lead to the image quality droping, reduce coding efficiency, for the removal of blocking, AVS standard adapts the loop filter technology.In this paper, based on the careful analysis of AVS standard loop filter algorithm, finished the hardware design of the loop filter. As the loop filter in strip-level, macro-level block boundary, pixel-level adaptive features, making loop filter's computational complexity is high, slow, so the pipeline design is used in macro block handling and boundary filtering, to improve the processing speed. At the same time using the same filter in order to saving of resources by the pixels redistribution of flat and vertical boundary.In this paper,we use th top-down design approach, dividing the sub-module. We do the simulation for each sub-module. At last we do FPGA synthesis and analyze the clock cycles required for the macro block filter. After testing, the design is operating normally and the result is correct in real-time decoding.