Optimization And Design Of Instruction Pipeline Of YHFT-DX High Performance DSP

DSP (Digital Signal Processor) is a special processor for digital signal processing, which is also the key technology in this domain. Now DSP has been widely used in domains such like communication, consumption electronic, industry control, military radar, spaceflight and so on. With the development of technology of these domains, more advance DSP processores are required. So the study of high performance DSP has important influence on these domains.YHFT-DX is a 32-bit fixed-point high performance DSP being designed by NUDT. Its architecture is very long instruction word (VLIW) and it can issues 8 instructions in a cycle. Its CPU will runs at the frequency of 600MHz and deliver 4800MIPS. Besides profound peripheral equipments are integrated on chip.The study of optimizing about pipeline points to two sides, that is how to improve code density and how to decrease the stall of pipeline caused by memory block.Improving code density not only can reduce the needs of memory, but also can cut down the memory accessing bandwidth owing to cache missing, so this technique can improve the performance of DSP and reduce the power consume of system bus. This article brings two techniques, nonalign dispatch and compact instruction, to improve code density. The compact ratio is up to 15% and 30% respectively. Nonalign technique can remove the bubble in code by the way of dispatching execute packet cross the boundary of fetch packet, but compact instruction technique reduces the code size using 16-bit instructions replacing part of 32-bit ones.The key point of YHFT-DX's Instruction Control Unit is whether it can deliver uninterrupted parallel instruction stream of high density. To implement uninterrupted parallel instruction stream delivery, a prefetch mechanism of fetch unit level was researched and designed, which greatly improved the pipeline efficiency. The time of executing standard testbench is 5.15% shorter on YHFT-DX than that on non-prefetch.At last, this article does much work on designing and improving YHFT-DX's verification environment, and applying assertion to our verification system to improve efficient of verification. Besides this article realize ASIC prototyping using FPGA and design perfect FPGA verification system.