The Design And Hardware Implementation Of H.264 Decoder

Accompanied by the boom of consumer electrical product, multimedia processing technique has widely progressed. Video compression technique is fully developed because of the emphasis of the high-tech field, then the new video compression standard H.264/AVC comes out. This new standard it will bring us high quality image. In the same time, the technique of semiconductor chip-design has gained a big boost, which makes the performance of IC higher than ever before. So the chip has becomes one of the most significant carrier of latest technology. Under this background, it is inevitable to use advanced SoC solution to implement the new video compression standardH.264/AVC decode SoC has a video part and an audio part, but the focus of this thesis is on the solution of video function. Since every project is based on the theory, this thesis starts with the introduction of video compression technique and the background of VLSI, this thesis puts the emphasis on the new technology and optimization. Next, this paper mainly describes the structure of H.264/AVC video decoder SOC, entropy decoder module design, and hardware implementation of intra predict module , platform based on FPGA .Then gives a detailed describe about the verification strategies and completion schemes.This thesis covers the front-end design flow of H.264/AVC decode SoC, and gives the solution including the key technology of multimedia processing. It will not only contribute to the development of information Industry, especially HDTV and digital TV technology, but also be significant to the practice of VLSI design methodology.