VLSI Design Of Macroblock In The Chip Of H.264 Decode

With the explosive growth of the demand for video and audio information, the pursuing of interactivity of video and audio over long-distance has been fashioned. In recent years, based on the develop of computer science, communication and networking, multimedia information which integrated audio, video, images, texts and data, has facilitated more and more people by bringing the joys of cyber-life, tele-medical and telecommunications, which shortened the distance over time and space. The key technology among these applications is video compressing, which brings many coding standards out.H.264 is a recently completed video compression standard which jointly developed by the ITU-T VCEG and the ISO/IEC MPEG standards committees. The standard provides much higher compression than earlier standards. It supports high efficient coding method of non-interlaced and interlaced video, and it can provides more acceptable visual quality than earlier standards at low bit rate.The H.264 video coding standard is analyzed in detail, and the further research of macroblock level in the decoder has been done. At first, parameter information of the macroblock is extracted from the bitstream sequence. Then the image data of macroblock can be calculated by these parameters and other image data.The circuit of H.264 decoder in macroblock level has been designed, including the circuit of decoding macroblock characteristic information, the circuit of decoding macroblock forecast information, the circuit of decoding macroblock remaining data. Each functional unit is designed respectively. Finally a control-unit is used to control all functional unit. This paper also completes the circuit of intra prediction in the H.264 decoder, including 16×16 intra prediction and 4×4 intra prediction. The VLSI circuit is described by the Verilog hardware description language. The VLSI circuit has been simulated and synthesised.