Based On Fpga-iso / Iec 18000-6c Of Rfid Reader Design

"Internet of Things", known as the driving force of global economic recovery and the third revolution of information technology, has an important role to economy and technology development. Nowadays, the development of Internet of Things has become a hotpot of competition of high technology and information technology industries among many countries. The United States ascends it to the national information technology development height, and China looks it as one of emerging industries of national information technology which will be focus on development. As one of the key technologies of Internet of Things, RFID technology has also been valued by governments and the IT staff in recent years. RFID industry in China started late, and was relatively backward, especially in UHF band. Therefore, developing a kind of reader on UHF with independent intellectual property and good performance is not only important for Chinese RFID technology development, but also for pushing the development of Internet of Things industrial and satisfaction the market's requirements. For those reasons above, a kind of RFID reader with 915MHz as its centerfrequency based on FPGA and ISO/IEC18000-6C protocol has been studied and achieved, and the main studies includes:Firstly, after concisely introduced the current UHF agreement, the detail of ISO/ IEC18000-6C protocol is elaborated.Secondly, the framework of entire reader design has been proposed. For the RF transceiver design, the functions and skill of all parts has been researched. Emission channel uses Digital Synthesis Chip Si4133 to produce carrier, make HMC284 to modulate, rely on SPA2118 to amplify, and apply antenna to transmit. Considering the characteristics of ASK modulation and receiver may has strong interference because transmitter and receiver uses the same antenna, I, Q two road diodes as detecting circuit are used. However, the detected signal has been amplified by amplifier, and been demodulated by the comparator. RF transceiver uses discrete components with simple design, easy test and low cost. Thirdly, the procession of baseband section has been researched, simulated and realized. It has been divided into several modules with different function which has been realized by internal logic resources of FPGA, including coding and decoding module, anti-collision module, calibration module, the protocol stack module and interface module, and so on. While FM0 decoding, because the received FM0 data may exist irregular pulse caused by environment noise or incomplete demodulation which due to imperfection of demodulation circuit, it uses pulse width decoder rather than the sampling pulse width decoder. Anti-collision is the technical bottleneck of the reader. After studied theory and process of anti-collision, a simple selection algorithm of Q-value has been proposed and applied.Finally, it uses system testing platform to test and extract data from the designed reader system. By analyzing the images and data, the conclusion that the reader can achieve the desired functional can be obtained.