Embedded In The Soc Nor Flash Ip Core Test To Achieve The Research

There are many factors for designing a SOC successfully, but the key factor for SOC yield is the yield of the embedded Flash. For improving the yield of embedded Flash, we should not only make sure the performance and testability of Flash IP in IC design phase, but also test the flash efficiently with external equipment in IC test phase.At the beginning of IC design phase, we should test, analyze and prove the characteristic of Flash IP, to make sure it meets the actual application. In IC design phase, we should re-design the IP interface according to the characteristic, test requirement and application requirement of the IP. These re-design is a challenge. If the re-design is advisable, the test controllability, test time and also operability of end user will be improved very much.After analysis, it is found that the Flash IP meets the performance requirement. Besides, Flash IP has Bit Line redundancy repair ability. If the repair function is made full use of, the yield will be emprove very much. For the controllabitily of Flash, we developed Flash test and program interface ourselves on the base of SPI bus protocol, which we use to control the Flash.On the base of four signals of SPI bus (CS, CLK, SDI, SDO), we added two more signals——PORV and VERIFYOK. After every byte is programmed in through SPI, the test module informs the chip to verify data itself by the two signals, and then the chip informs the test module with verification results by the two signals. Therefore, the test module needn't to verify data, the test controllability and the test time are improved very much. Phisical characteristic of every flash cell is different, and the two signals can adjust program time dynamically. So the programming flexibleness and efficiency are improved, and the balance between flash yield and programming time can be found easyly.For the external test module design, firstly we should think of testing the yield reliably, second we should think of saving test time and improving test yield, at last we should think of operability of the module to make engineers use it conveniently. If the test module use Bit Line redundancy repair algorithm to test and repair the Flash, the yield will be improved very much.In the test procedure, software drives test module hardware to program certain data into the flash, and then read out the data for verification. So the software needs to perform a complicated test flow. Besides, according to verification information, it analyzes the characteristic of failure data. Using the statistical information of failure data and a certain algorithm, it calls redundancy repair function and achieve flash test and repairment. With the test module, the flash yield can be improved by 8.3 percent.On the base of the existing test and program interface, if we re-develop the test module, there will be an innovation on test, program and application. When we are re-develping, the existing hardware architecture and software driver is helpful, the developing can be faster.