Research And Implementation Of SoC Embedded Flash Built-in Self Test Method

Modern society is an information society, which means the storage of information is becoming more and more important. As a result, memory is playing a great role in our lives. On a SoC chip, the proportion of memory is gradually increasing. It is estimated that by2016, more than95%of the total area of the SoC chip will be occupied by embedded memory. Among all the memories, Flash as a nonvolatile memory, with its characteristics of the data is maintained even after power-down is being widely used. With the decreasing of the feature size of semiconductor devices, more and more types of fault occur in Flash memory, which makes its measurement becomes more and more difficult. In addition, due to the increase of SoC pins and speed, the cost of test machine is becoming more and more expensive. To solve the problems mentioned above, this paper researches the built-in self test method to test SoC embedded Flash.This paper introduces the basic structure and working principle of the Flash memory. Combined with its structure and working principle, this paper does a research about the inherent faults of memory:the stuck-at fault, transition fault, bridging faults, coupling faults and address decoder fault, the peculiar faults of Flash memory: DC-Programming, DC-Erasure, Drain Disturbance and so on. The research about the faults’generation mechanism helps us get a better understanding of Flash test.Secondly, this paper carries out in-depth research on the memory test method. Analyses the complexity and fault coverage of several common memory algorithms:the MSCAN algorithm (Memory Scan), GALPAT (Galloping Pattern) algorithm, Checkboard algorithm and March and its derivative algorithms. Because of the special structure and access mechanism of the Flash memory, this paper improves the Checkboard algorithm and applies it to the Flash memory test. This paper ultimately determines to use the improved Checkboard algorithm and March-FT algorithm as Flash memory test algorithms, and put them into implementation.Finally, this paper carries out the research about the parallel interface test plan, semi-parallel interface test plan and serial interface test plan, and decides to use the serial interface test plan as this paper’s test plan. This plan can reduce the test cost significantly. Combined with the algorithm researched, this paper designs and implements the built-in self test circuit. After simulation and verification by Modelsim, the architecture and function of the circuit proved to be correct.