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Research On Background Error Correction Method Of Time Interleaved Analog - To - Digital Converter

Posted on:2014-04-19Degree:MasterType:Thesis
Country:ChinaCandidate:Y W ZhangFull Text:PDF
GTID:2208330434966195Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The high-performanced mixed analog-digital integrated circuit is the key technology in the next generation ultra-band wireless communication system. Analog-to-digital converter (ADC) is the critical device of the communication physical layer. To some certain extent, its bandwidth, speed, accuracy, cost, power and reliability determine the performance and functionality of the wireless base stations and the terminals.When the structure of a single ADC has reached the limit of the condition of design and process, parallelization is an effective method to break the constraints on the sampling rate. A time-interleaved ADC has several paralleled channel ADCs (Sub-ADC), which sample the input in turn. It can increase the overall sampling rate of the entire ADC while maintain high precision.However, in the actual cases, there are several inidealities between the channels of the time-interleaved ADC, such as offset mismatch, gain error and sample-time error, which greatly reduce the resolution of the time-interleaved ADC. Therefore these mismatches must be calibrated.This paper presents a correlation-based digital background sample-time error calibration method. It can be applied to most situations, and it expands the input signal conditions to wide-sense stationary signal which is common in communication systems. It can be also applied to any number of channels. In addition, the calibration circuit is so simple that it has small hardware cost and low power consumption.The experiment of the digital background calibration method proposed in this paper is based on a2-channel14-bit200-MSps time-interleaved ADC prototype chip and a Xilinx Virtex4FPGA board. The experiment results show that the calibration method completely eliminates the constraints of the sample-time error on the overall performance of the ADC. The spurious-free dynamic range (SFDR) increases30dB after calibration, the signal-to-noise-and-distortion ratio (SNDR) increases15dB and the effective-number-of-bits (ENOB) increases2-3-bit.
Keywords/Search Tags:Sample-time error, Time-inter leaved Analog-to-digial Convertor, Calibration
PDF Full Text Request
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