Based On The Rtl Description Of The Combinational Circuit Automatic Test Pattern Generation Technology Research

Hardware description language (HDL) has been widely used in the design of IC. Right between behavior level and gate level, RTL (Register Transfer Level) HDL description involves both the behavior information and the detailed structural implementation of the circuit. This fact has made it possible to promote or reform structure-based test methods at the RTL. At the same time, it is also possible now to produce new test techniques through combining test methods at the behavior level with those based on the structure. In recent years, various behavioral and structural schemes have been proposed. These techniques may target gate-level ATPG or symbolic testing. Some others are based on extracting functional information from circuit. This paper proposed a new methodology of using structurally similar modules constructed by compressing vectors in a circuit. A gate-level test generator is used to generate test vectors for the module under test, then these vectors are adjusted and assembled into system test patterns using a mapping method. This method is mainly based on structure-based test techniques, and also it combines the deterministic algorithm with random test generating techniques. This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compressing the bit-width of vectored vectors in the original circuit. BSC shrinks the scale of the original circuit, thus improving the ATPC efficiency. Test patterns are derived from adjustment and assembling of precomputed sub-circuit test sets. Based on the deterministic algorithm, the ATPG method presented in this paper combines deterministic algorithms and undetermined methods. Experimental results show its advantages. This paper also introduces a Verilog HDL compiler for ISCAS-85/89 Benchmarks as a utility for the study of RTL combination circuits. On the basis of the analysis of features of Verilog HDL and RTL description, this paper shows the method of the construction of the module library and the conversion from RTL HDL description to gate-level description.