The Algorithm Of Digital Video Processing Chip Research

People hope for the higher and higher quality of TV program with the life improving, and the traditional TV system can't fit for this requirement, it's obviously attractive if we can find a solution that can improve the quality of TV program, as well doesn't cost too much. The image processing technology can fit for this task now, there are several methods to improve the image quality of TV signal, such as de-interlacing, frame rate up-conversion, image enhancement, noise reduction, and so on. The processing can convert the interlaced, low scan rate video signal to the progressive, high scan rate signal which has high image quality and high SNR(signal-noise-rate), to satisfy the need of the people.We will introduce the theory of video post-processing in this paper first, then describe 3-D recursive searching block-matching motion estimation algorithm proposed by Gerard et al. This algorithm can estimate the true motion of the objects that are required by the motion compensated video format conversion, it has a very low hardware complexity, the result of motion estimator will be used by the latter de-interlacing and frame rate up-conversion processing.After all kinds of de-interlacing algorithm including their advantage and disadvantage are analyzed, a new edge protected, motion compensated de-interlacing algorithm is proposed, in this algorithm, some improvements are added into the time recursive motion compensated de-interlacing algorithms proposed by woods et al. The improvements include an edge orientation detector, a median pass filter based on the edge orientation, and a high pass filter from the previous field to reduce the alias introduced by the median pass filter. This new algorithm performs better than the time recursive method. After that, the frame rate up-conversion algorithm is proposed. We will continue improving the quality of image by a median pass filter, edge enhancement processing and then color space conversion is proposed. At last the architecture of digital video post-processing chip is proposed.