Based On The Hardware Description Language And SOPC Cycle Error Correction Code Design And Implementation Of The Codec

The subject described in this paper is part work of the development of Communication Theory Experiment Unit. The equipment is a lab tool for students majoring in Communication Engineering and similar ones while they are learning the course Communication Theory. The usual experiments in the course as phase lock loop, cyclical error_correct coder and decoder, bit syncronization, frame syncronization are equipped with the tool. The equipment has been successfully designed in a traditional way. This paper focuses its upgrading. The product is supposed to be designed in a way such that all the experiment modules could be integrated in one programmable logic device (PLD). The advantage will be chip number reducing and upgrading ability increasing. The designs for every experiment modules would be implemented in the TOP-DOWN (from top to down) way.This paper involves the task of rebuilding cyclical error_correct coder and decodert.Two realizations are described in this paper. Firtly the VHDL based design for realizing cyclical error_correct coder and decoder is introduced. It is a realization of the cyclical error_correct coder and decoder with the EDA tools by using VHDL. Starting from the "top" ie its logic function description of the cyclical error_correct coder and decoder, the desired logic functions have been realized with VHDL.The process includes compilation, synthesis and simulation with EDA tools. The results show that the design can meet the required needs. Furthermore to realize same kind but different values of n and k of a (n,k) cyclical error_correct coder and decoder, the only thing that has to do is simply changing the corresponding VHDL sentences. This function greatly reduces time and resources of the circuit rebuilding.Secondly the process of SOPC design is discussed on implementing cyclical error_correct coder and decoder. With the development of programmable logic device, it is not difficult that SOPC system is realized by embed microprocessor core in an FPGA. The SOPC has both high flexibility of microprocessor and user programmability. So far, SOPC is becoming a trand of morden electronic design. The microprocessor core and the PLD chip used in this paper are respectively a 32 bit MicroBlaze and VirtexII provided by Xilinx.Embedded Development Kit (EDK) provided by Xilinx is used as a EDA tool as well. Before EDK work, the C programs of cyclical error_correct coder and decoder are written, and corresponding logic functions are realized under MS-DOS environment.Then the SOPC based design is realized on a VirtexII chip.