Based On The Fpga Before The Fec Algorithm And Circuit Design

This dissertation researches the arithmetic and the circuit implementation of Forward Error Correction (FEC) in digital audio wireless transmission. It introduces an implementation based on Altera's FPGA Cyclone. This project chooses VerilogHDL. The IP core's synthesis, place route and assemble are based on develop tool QuartusII4.2. The timing simulation is based on Modelsim. At last, the IP is downloaded in develop kit, and the circuit verification and test is done. First, the dissertaion introduces the plan of the FEC system. Then it introduces the master plan, including the architecture of the system, the module dividing, the design method and the coding style. After that, the dissertaion gives out the detail of each module also with the testing data, the implementing results and the timing simulation waveform. And it gives a detailed describe of the downloading and verification on hardware. This dissertaion gives basic arithmetic and solutions based on FPGA and HDL to the key functional modules of FEC, such as Reed-Solomon codec, interleaver, deinterleaver and peripheral circuits. While designing the system, we spent a lot of time in considering how to divide and define each module and how to coordinate and interconnect these modules. We followed the top-down method to design. First we defined the top module, then divided the top module into several independent small units. As for the interconnection of each module, we defined the interface signal to communicate between them, and the internal timing of the module was control1ed by states machine. When we was constructing the code, we payed much attention to hardware resource spending and concurrent executable ability of the VerilogHDL to make the design close to the hardware working way, so we could get a high speed with a low hardware spending to satisfy the demand of the cost, performance and practicability. It also gives out some reference for the future SOC.