Design And Implementation Of Multi-protocol Fast Ethernet Line Interface

IPv6 protocol is the certain trend of the next generation networks, on the other hand it will takes a long time for IPv4's dropping out, in other words IPv6 will be concurrent with IPv4 for a long period. So it is urgent affair to research and develop dual-stack router that can compatible IPv4 with IPv6. The Terabit router of the key project of "863" research and develop dual-stack core router that can supports IPv4/v6 protocol, MPLS protocol and have ability of IP multicast. 100M Ethernet circuit interface is one of its important interface type. According with the function demands of the Terabit router system for this interface and basing on the research of the 100M Ethernet specification, this dissertation's aim is to design a kind of hardware-implemented scheme of the 100M Ethernet linecard that can supports several protocols mentioned above. Aiming at some diffcult problem such as line speed routing lookup, low latency Round Robin algorithm, multiple duplication, clog-free demands of the MAC layer's chip etc, the scheme provides the concrete solution and through tests or hardware realization proved its exactness and dependability. The main work of this thesis is as follows:We divided the whole subsystem into seceral modules and specified the function of each module according to the function demands of the Terabit router system and the Fast Ethernet protocol specification. Based on these works,We put forward our hardware-implimented scheme.Put forward a dual-stack routing lookup scheme called "Segment Storing Cam+SRAM High Speed Routing Lookup Mechanism"(It has been issued by the magazine "Computer Engineering and Applications"), the mechanism proposed a series of new ideas about routing lookup, such as "the key words and the results were stored separately", "using the longest prefix as the key words", "directly lookup the MAC address according to the next hop IP address", "supporting compatible IPv4 routing lookup" etc, which reduced the number of times of looking up, saved the time and decreased the design cost. It's not only suitable for linecard routing design, but also suitable for transmitting module.A mechanism of clog-free is proposed to MAC layer chip for the flaw that it can't directly extend its buffer capability. This mothod can reduce the losing packet phenomenon caused by FIFO overflow by connecting an external FIFO array, at same time it can resolves the problem that the sending speed don't compatible with the receiving speed and so keep from the early losing packet caused by the queue header blocked.A modified low-delay algorithm for DRR is proposed based on the whole packet scheduling. By partitioning a big service into two or more small services, this algorithm can shorten the delay and big burst caused by a too long packet on one port. I experimentally demonstrate theeligible of modified algorithm and estimate the partitioning threshold according to the statistic distribution of length of network packet.Besides, with the experiences of precedents, a design for multi-protocol Fast Ethernet interface running and debugging was propoesd. After pointing out that the job of running and debugging design should have been done as soon as the scheme begin to be designed, the author described in detail the loop design used in this scheme. In the end, we tested the system latency, proved the exactness and dependability of the scheme.