Hardware Design And Implementation Of High-speed Image Data Receiving System

In this dissertation, the hardware of the high-speed image data receiving module in a real time viewing system is mainly designed. In this system, high performance as well as low power consumption and low cost about FPGA/CPLD are taken advantage of. And the high speed (up to 160MHz) circuit design is implemented. At the same time, the signal integrity about the key circuit is simulated with the Hyperlynx software. With which the circuit performation is enhanced, the debugging time and the cost are reduced.This system is applied in the image data receiving portion. In order to debug system conveniencely, a signal source card and a data receiving card with PCI interface are designed separately. The core of the signal source card is XC95144XL. It controls reading the image data from the PC and then sent out via the SMA interface in LVDS format or BNC interface in TTL format. The core of the receiving card is XC3S200. It input the LVDS data via the SMA interface. After entering the receiving card, the data are processed as follow:First, the synchronization data are picked up. Then the untiscrambling process is accomplished. At last, the image data are sent into PC via PCI interface. The system application program in the PC perform the decompress process. The final data are sent to the display, for the purpose of real time viewing. At the same time, the receiving data are saved into the harddisk, for the purpose of analyzing and displaying those data at a later time.In this dissertation, the signal integrity problem encountered in the high speed circuit design is analyzed theoretically. Both pre-simulation and post-simulation instruct layouting PCB board and comfirming the values of the resistance and capacitance.