Pipelined Adc Correction Circuit Research And Design

Analog-to-Digital Converters (ADCS) are widely used electronic components .The demands of high quality modern signal processing systems are driving the development of ADCS towards higher speeds and lower power dissipations. By calibrating and compensating existing ADC devices, the ADC performance can be improved effectively.Based on studying of the pipeline ADC's architecture and error mechanisms, an improved calibration scheme for a 10-bit 100MHz ADC is presented. The goal of this compensation scheme is to make the ADC tolerant of comparator offsets and can detect input signals'overflow and achieve the desired linearity。Dominant error mechanisms in the S/H, sub-ADC, sub-DAC and gain stage are defined and characterized for an arbitrary stage in the pipeline. The functional descriptions of these error mechanisms which can reveal how errors of various blocks in ADC affect the output sample are provided; analyses show that the first stage of the converter is dominant in a pipeline. According to research of Redundant Signed Digit (RSD) calibration theory of pipelined ADC,a novel Out of Range Detection RSD technique is provided. When input signal is out of the ADC's range, the technique can detect this situation and the wrong output word is avoided. The technique is realized by modifying the first stage sub-ADC and the encode logic and adding two parts digital circuits. Under 0.35um Si-CMOS process, considering the trade off of accuracy and speed in the ADC, 2.5-bit were converted in the first stage of the pipeline. Using the improved calibration scheme and full difference structure and bottom-plant sampling technique to reduce the errors of the 10-bit (2.5+1.5×5+3), 100Msample/s pipeline ADC. Two output data forms are designed: Two's Complements and Offset Binary. Based on a 0.35μm SMIC Si-CMOS model the circuit is simulated using HSPICE. The slope signal analyses and sinusoidal signal analyses show that the DNL≤±1/2LSB, at 49.902 MHz input frequency and 100MHz sampling frequency, SFDR is 75.5dB and the OR output can detect correctly whether the input signal is overflow and the system has good linearity.