Ldpc Test Platform Time-domain Synchronization Algorithm And Fpga Realization

The merged blue print for digital terrestrial television broadcasting which suits to the developing status of DTV in China is a standard of the Chinese DTV-T. LDPC code is used as FEC. The narrowband LDPC code platform is constructed to test the ratio error of the LDPC decoder, for the restriction of the software debugging.Usually in OFDM system, the time-domain synchronization in the platform is the symbol-frequency synchronization using PN-sequence preambles. Its algorithm has been designed based on the requirement of platform, and validated by Matlab simulation. Then the Verilog program has been designed based on this algorithm. Finally, the hardware Debugging has been done.In this thesis, the developing status of DTV is introduced firstly. The merged blue print for digital terrestrial television broadcasting in China and the structure of platform is introduced following. In the project of constructing the platform, the design of the time-domian synchronization algorithm is in the charge of me, which has been realized on FPGA. It is introduced detailedly in chapter 3 and chapter 4. Additionally, the design of LDPC decoder based on FPGA is another part of the project. It is introduced briefly in the end of chapter 2. This thesis is summared in Chapter 5. The main work described in this project is listed as follows:1. Design the time-domain synchronization algorithm of platform, and simulate it in Matlab.2. Design the Verilog program and finish all kinds of simulation.3. Debug the Verilog program on the hardware platform.4. Design LDPC-decoder based on FPGA.