Based On The Fpga Design Of The Distributed Transmission Line Fault Recorder

The trend of today's power system is digital device and interlink of networks, and the perfonnance of power system is more complex than before. The increasingly complexity of power system requires much higher demand to fault recorder which is as necessary as power system fault analysis. The development of FPGA technology and embedded system provides necessary conditions for improving the performance of fault recorder.Firstly, a scheme on implementing high performance fault recorder of distributed transmission line based on technologies above is proposed in this dissertation. Structures and functions of the hardware and software of the device are analyzed in brief. A design of data acquisition unit based on FPGA and AD7656 is presented to solve the problems of high precision and high speed of data acquisition unit in fault recorders. Then, a design of SDRAM controller based on FPGA with an embedded PowerPC microprocessor is developed to solve the problems of mass fault data storage. And the SDRAM controller is simulated with Modelsim6.0. A series of problems about constructing an embedded system on the microprocessor which embedded a PowerPC core are studied. Finally, some problems about fault range finding algorithm of traveling wave applied in fault recorders of distributed transmission line are discussed.