Mobile Phone Tft-lcd Driver Chip Sram Design

All kinds of memory will be embedded in today's SoC system in order to improve the system's performance, especially the static random access memory(SRAM). It will be the chief factor when memory is selected since SRAM is compatible to the standard CMOS process. These memory possess the great proportion of the whole chipset both in the energy consumption and in the chipset area. In order to lower down MPU's burden, SRAM is embedded in the TFT-LCD driver. MPU completes some operation to a frame of display data stored by SRAM by setting instructions.The research work of the dissertation is part of National "863" project named Research on TFT-LCD Display Driver IC for Colored Display Cellular Phone, which is carried out by NWPU Aviation Micro-Electronics Center. There are two main parts, including the design of SRAM and its control circuit.First, the principle of divided word line and hierarchical word decoding is analyzed to divide the SRAM body into four parts. Then the memory cell's size is designed by SNM simulation. And designed the decoder both normal write and high speed write compatible using two level decoding. At last, based on characteristic of read data operation from SRAM, a precharge circuit using charge-recycling has been employed, and lower down the dissipation durig precharge. Partly pre-charge technologies make sure there was enough time to precharge.SRAM control circuit supplies the address, timing and operations to display data, such as mask, dummy, high speed write. The high speed write is realized by generating high speed write timing in controller, controlling address in decoder, and storing data in write/read driver. There are two SRAM operations: MPU write/read and line scan, and they will conflict when the two operations operate SRAM at the same time. A MPU first conflict solution circuit has been designed.The results of NanoSim simulation show that the reading and writing times of SRAM are less than 8ns, and the static power dissipation is 1.1mw and the dynamic power dissipation is less than 4mw at operating frequency of 3.8MHz.