Part Of The Qc-of Ldpc Parallel Decoder Design And Implementation

Low density parity check (LDPC) code is proposed in 1962 by Gallager, which is one kind of the near Shannon Limitation error correction code. In order to achieve better performance, the random sparse parity check matrix is generally used in the LDPC researches. But the random architecture of check matrix leads to huge resource requirement for LDPC hardware implementation. The quasi-cyclic (QC-LDPC) is one of practical solutions for this issue.This thesis focuses on the hardware implementation issues of QC-LDPC decoder on the FPAG platform with as less as possible logic resources. The fundamental information about QC-LDPC, such as definition, construction and performance, is introduced first. The BP and BP-based algorithms used in this thesis are also introduced. In order to simplify the implementation, a revised UMP BP-based algorithm is proposed in this thesis with little performance loss.3 types of decoder architecture, serial, parallel and partially parallel, are discussed in this thesis. The Partially-Parallel architecture is chosen for the trade off between decoding speed and resource requirement. And the parallel degree of the Partially-Parallel is determined by the characteristics of QC-LDPC codes'parity check matrix.The main contribution of this thesis is that a point-based circuit is proposed for the minimum value and the next minimum value search. Compared with classical schemes, the proposed circuit required the less logic resources for BP-based algorithm, especially for the parity check matrix with large row weights.The QC-LDPC decoder implemented with 2152 slices and 34 Block RAMs to obtain 9.375Mbps throughout. Compared with Random LDPC decoder with similar code length, code ratio and performance, the QC-LDPC decoder increases 44.2% on data throughout, while it reduces 27.5% on slice and 37% on Block RAM. As a typical kind of the LDPC codes with algebraic structure, QC-LDPC will surely get more and more attention in the future.