High-voltage Pmos Device Threshold Voltage Stability To Improve The Process

The device design, the electrical characteristics, and process integration of the high-voltage CMOS devices are quite different comparing with standard CMOS devices, which makes it difficult to establish stable electrical characteristics in the production of the high-voltage CMOS devices. The threshold voltage of high-voltage PMOS devices is a sensitive and critical parameter for process stability. Its deviation will lead to degrading of the end-product electrical performance and increasing of wafer scrap rates and manufacture cost. The purpose for this thesis is to improve the stability of the threshold voltage of high-voltage PMOS devices by decrease its standard deviations. The study was focused on the effects of the major process steps on the stability of the threshold voltage.1) The effects of the beam energy and dosage of the B~+ ion implantation on the threshold voltage was studied. A 5% change of implantation dosage has resulted in 10% change on the threshold voltage of high-voltage PMOS devices. The beam energy was found to affect the stability of the threshold voltage. Ion implantation with higher beam energy has decreased the deviation of the implantation depth thus are beneficial for improving the threshold-voltage stability.2) High-temperature growth conditions of the gate oxide were found to have a great impact on the stability of the implanted B~+. The threshold-voltage stability was improved by exchanging the sequence of gate oxide growth and ion implantation.3) The effects of the RTA (Rapid Thermal Annealing) steps of the front-end process on the activity of implanted B~+ were discussed. The threshold-voltage stability was unaffected as the activity of implanted B~+ was not altered by annealing below 850℃.